Integrated circuits including metal-oxide-semiconductor (MOS) transistors receive input signals and transfer output signals in the form of a voltage. These devices are typically made with very small device dimensions in order to maximize the amount of circuitry that can be implemented on the integrated circuit and to allow the circuitry to operate at high frequencies yet with minimal power demands. A problem with these devices, however, is their sensitivity to damage from electrostatic discharge (ESD) applied to the input terminals, output terminals or to internal circuit nodes of the integrated circuit.
As is well known, ESD events, although brief, may exhibit relatively large currents, on the order of amperes. In order to combat problems associated with ESD events, manufacturers of MOS devices design protection devices that provide paths through which to discharge nodes rapidly so that the voltage on the nodes may be clamped to a safe level. Protection devices may be positioned between the input buffer or output buffer pads of a device and a source of reference potential (e.g., ground) to quickly conduct the ESD current away from the devices that may be harmed.
Turning now to FIG. 1, illustrated is a top-plan view of one such ESD protection device 100. The ESD protection device 100 is implemented as an N-channel MOS transistor having source and drain regions and a gate electrode over a channel region that separates the source and drain regions. Although the device is implemented as an MOS transistor, it operates, in ESD protection mode as a parasitic bipolar transistor having a collector region corresponding to the drain region, an emitter region corresponding to the source region and a base region corresponding to the channel region. In a typical configuration, the gate electrode is tied to a source of reference potential (e.g., ground) either by a direct connection or through a resistive connection. As is well known, when the potential between the collector and the emitter (Vce) of the bipolar transistor becomes greater than a predetermined voltage, known as the trigger voltage, the voltage Vce snaps back to a lower value. The device clamps the voltage at this lower value, known as the holding voltage. In this conduction mode, the transistor presents very low impedance and, thus, conducts any current to ground.
The ESD protection device 100 shown in FIG. 1 includes multiple channels through which the relatively high ESD currents may be conducted in order to reduce the voltage and current stress on the device. Each channel is defined by a metal connecting terminal 128, in the drain region 120 of the transistor 110, and a corresponding metal connecting terminal 138 in the source region 130 of the transistor 110. Connecting terminals 128, 138 are connected to solid metal connections 140. Metal openings or slots 150 are sometimes required for various process reasons.
Ideally, during an ESD condition, substantially equal “current paths” are established between each pair of connecting terminals 128, 138, creating multiple nonintersecting and nondiscriminating paths to discharge the ESD current. However, due to the snapback issues mentioned above, such an ideal situation rarely, if ever, occurs. For instance, the aforementioned snapback makes it hard for NMOS transistors to distribute current evenly among the channels, because, as soon as snap-back happens, Vce on one turned-on channel drops to a holding voltage, which is lower than the trigger voltage of the other channels and therefore, other channels do not have a chance to turn on. Accordingly, snapback is a significant problem for the multiple channels in an ESD event.
Another trend in semiconductor processing is to apply silicide to the source and drain regions of MOS transistors in order to improve their performance. Silicided regions typically exhibit lower surface resistance than the doped silicon that forms the source and drain regions. Applying silicide to the source and drain regions of an ESD protection device, however, may affect the performance of the device. Because the silicide may have a relatively rough edge next to the gate, this may lead to high local electrical fields and to degradation of the edges by high current densities (and corresponding increases in temperature). Because the silicide has a relatively low sheet resistance, it may also kill whatever ballasting existed between drain contact and gate and make the multiple channel snapback issue even worse.
Turning now to FIG. 2, illustrated is a plan view of an ESD protection device 200, which uses blocking of the silicide to introduce ballasting. The ESD protection device 200 shown in FIG. 2 containing discrete connecting terminals 228 and 238 has the silicided blocked on both the source side and the drain side. Ballasting occurs due to the aspect ratio of the width of the structure to the length of the regions in which silicide is not applied. One disadvantage of the configuration depicted in FIG. 2 is that the additional processing steps required to form devices in which silicide is selectively applied are costly.
One other way to solve snapback issue in NMOS type ESD protection is to use external ballasting resistors on the drain fingers in a multiple finger NMOS. When one of the drain fingers turns on and snaps back, the product of its current and ballasting resistance on this finger is going to generate a voltage high enough to trigger other fingers and therefore enable all the fingers to evenly conduct ESD current. This efficiently increases ESD robustness of NMOS devices. Obviously, a disadvantage of this solution is it costs too much silicon area (from ballast resistors).
Attempts also have been made to provide ESD protection, as described in U.S. Pat. No. 5,763,919, by implementing a MOS transistor array structure having dispersed parallel discharge paths. These dispersed parallel discharge paths are formed in the n-well regions and in the N+ drain regions of the structure. The dispersed N+ drain regions are defined by local oxidation or shallow trench isolation (STI). The part of the N+ to substrate junction close to the local oxidation or STI interface may exhibit mechanical stress causing, among other things, electric field focal points, current leakage and susceptibility to breakdown. This structure also has non-linear discharge path resistance due to the N-well, and the performance of the structure is dependent upon the diffusion/well resistance. Another feature of this structure is that the dispersed parallel discharge paths are not isolated from the substrate, thus causing potential breakdown to the substrate (dispersed N+ drain regions) and adding undesirable additional parasitic capacitance (dispersed N+ regions and N-well regions).
Accordingly, what is needed in the art is an ESD protection circuit that provides the benefits of traditional ESD protection circuit without the drawbacks.